The CMSG120N013MDG hybrid module is specified at up to 260 A at 25°C and 130 A at 100°C, illustrating the thermal/current trade-offs designers must quantify when using Si/SiC hybrid switches. This report explains the key Si/SiC performance metrics for the CMSG120N013MDG, how those metrics are measured, what the numbers imply for system design, and the recommended validation steps engineers should follow. The intent is a data-focused, repeatable test approach that yields comparable conduction, switching and thermal metrics for practical system decisions.

Readers should expect concrete measurement guidance (double-pulse, steady-state thermal mapping), recommended plots and pass/fail thresholds for reliability tests. The report references established industry test practices and published device-reliability literature from recognized laboratories and trade groups to support measurement choices without linking externally; engineers are encouraged to consult device manufacturers’ datasheets and independent module-performance analyses for raw data.

1 — Background: What the CMSG120N013MDG Is and Why Si/SiC Hybrids Matter

Module architecture & intended applications

The CMSG120N013MDG is a hybrid power module that pairs a silicon IGBT conduction device with a SiC MOSFET switching or auxiliary leg in a monolithic package (SOT‑227 style thermal footprint) rated for 1200 V operation. The hybrid combines the lower conduction drop of a tuned Si IGBT with the fast switching capability and high-voltage robustness of SiC, targeting PFC stages, solar inverters, motor drives and EV onboard chargers. Compared with full SiC, the hybrid reduces BOM cost and gate‑drive complexity in some topologies while offering improved overall efficiency compared with legacy Si-only modules; compared with full Si solutions, it lowers switching losses at higher frequencies but introduces mixed-device thermal coupling that designers must manage.

Key datasheet ratings to extract & validate

Priority datasheet values to extract are: rated continuous current Id (260 A @ 25°C, 130 A @ 100°C), breakdown voltage (VCE(sat) / VDS specification), on-state conduction parameters (VCE(sat) for the IGBT leg, Rds(on) or on-resistance for the SiC leg), switching energy figures (Eon/Eoff or specified switching loss), thermal resistances (Rth(j‑c) and Rth(c‑a)) and SOA limits including short-circuit and surge ratings. Engineers should build a short checklist to validate these in the lab: reproduce the quoted current vs temperature ratings, confirm Rth with steady-state power sweeps, and measure switching energy with a controlled double‑pulse test to compare to catalog Eon/Eoff conditions.

System-level benefits and limitations

Hybrid modules excel where mixed goals exist: they reduce conduction loss compared to large-area IGBT-only stacks and reduce switching loss relative to Si-only hard-switching designs, delivering improved efficiency at moderate switching frequencies. Limitations include gate-drive partitioning (different optimal gate charge handling for Si vs SiC), potentially higher EMI if not tuned, and tighter thermal coupling constraints because one device’s dissipation can raise adjacent junctions. Baseline system metrics to track during evaluation are: peak efficiency at rated power, EMI spectra around switching transitions, thermal derating curves across ambient temperature, and gate-drive current budgets.

2 — Electrical Performance Metrics: Conduction & Switching

Conduction losses and on-state resistance

Conduction metrics are device- and leg-dependent: the IGBT leg is characterized by VCE(sat) as a function of collector current and junction temperature, while the SiC leg is described by Rds(on) vs temperature. For module-level conduction loss, sum resistive drops in the current path and include contact and busbar losses: Pcond ≈ I^2·(Rpath + Rds(on)) for SiC-dominant paths, and Pcond ≈ I·VCE(sat) for IGBT conduction. For measurement, specify Tj, use DC or pulsed currents with known duty to avoid self-heating during sampling, and log the current waveform shape. Present measured vs catalog values with identical test conditions (ambient, thermal interface, measurement method) and include plots of conduction loss vs current at 25°C and 100°C to visualize derating.

Switching energy and dynamic behavior

Switching metrics (Eon, Eoff, rise/fall times) quantify energy dissipated per transition under specified VDC, Id and gate-drive conditions. The SiC leg typically shows lower Eon/Eoff at matched voltages and faster dV/dt and dI/dt; the mixed-module waveform will therefore reflect asymmetric transitions and possible increased ringing. Recommended test setup is a controlled double-pulse fixture with defined load inductance, calibrated voltage and current probes, and repeatable snubber/gate resistor settings. Track dV/dt and dI/dt, parasitic ringing amplitude/frequency, and EMI-relevant metrics; capture switching energy vs voltage/current and present energy curves for gate-resistor sweeps to choose optimal Rg for the required EMI/efficiency balance.

Gate drive & turn-on/turn-off tuning

Hybrid gate requirements are often heterogeneous: the SiC device benefits from low loop inductance and carefully chosen gate resistance to limit dV/dt, while the IGBT leg needs conservative gate charge control to manage tail currents. Best practices are separate gate paths with independent Rg, power-limited gate drivers, and active clamping as needed. Actionable tuning steps: start with low-energy double-pulse characterization, sweep Rg in coarse steps to identify ringing thresholds, then fine-tune to meet switching-loss and overshoot targets; document final settings and retest under thermal load to ensure stability across temperature.

3 — Thermal & Reliability Metrics

Junction-to-case and case-to-ambient thermal paths

Thermal performance is governed by Rth(j‑c) and Rth(c‑a); in hybrids, thermal coupling between Si and SiC junctions raises local hotspot risk. Recommended measurements include steady-state power-loss mapping (increment power while measuring case and top-side temperatures), infrared thermography for spatial temperature distribution, and direct junction monitoring if possible. Use a calibrated thermal interface material and consistent torque on module screws for repeatable Rth(c‑a) assessments. Produce thermal maps at multiple power levels to identify hot spots and validate heatsink designs.

Thermal derating and safe operating area (SOA)

Translate junction-temperature limits into usable derating curves: for example, the published 260 A @ 25°C derates to 130 A @ 100°C — plot that linear or manufacturer-provided derating and apply safety margins for continuous vs pulsed duty. Recommended derating rules: use conservative margins (10–20%) for continuous operation and higher margins for mission profiles with frequent thermal cycling. For pulsed operation, define duty-cycle-dependent current limits and verify with thermal transient testing to avoid cumulative heating that exceeds junction limits.

Lifetime & robustness indicators

Key reliability tests are thermal cycling, power cycling, solder fatigue evaluation, short-circuit withstand and mission-profile stress tests. Pass/fail thresholds should be defined relative to expected mission life (e.g., number of thermal cycles to a defined percentage increase in on-resistance or shift in switching energy). Maintain monitoring logs for junction temperature estimates, forward-voltage shifts and leakage current trends; early degradation often appears as incremental conduction increase or intermittent switching anomalies revealed in long-duration burn-in.

4 — Test Methodology & Data Presentation

Recommended test bench and measurement chain

A robust bench includes: programmable DC load, double-pulse tester (with controlled Ltest), high-speed oscilloscope (≥500 MHz recommended for switching edges), calibrated current probes and high-voltage probes, a thermal camera and a gate driver with adjustable Rg and measured drive current capability. Best practices: keep probe grounding short and consistent, verify probe bandwidth and calibration, use averaging only where appropriate, and document repeatability by running multiple identical sweeps and reporting standard deviation for key metrics.

Standardized test protocols to compare modules

To compare modules fairly, adopt a repeatable protocol: ambient control (thermal chamber when possible), preconditioning cycles, defined current/voltage sweep steps and temperature points (nominal 25°C, mid 75°C, elevated 100°C). Include standardized double-pulse parameters (Vdc, Ipk, Ltest, gate resistances) and capture efficiency vs load, switching energy vs voltage/current, and thermal maps. Publish full test conditions and fixtures so others can reproduce results.

How to present uncertainty and normalize results

Document measurement tolerances and uncertainty sources: probe insertion error, oscilloscope bandwidth limits, thermography emissivity assumptions, and fixture parasitics. Normalize losses per kW of processed power or per unit area when comparing modules with different footprints. Call out how gate-drive settings or snubber networks influenced results and provide normalized baselines (e.g., Eon/Eoff at Rg = X Ω) to enable apples-to-apples comparisons.

5 — Comparative Case Studies: CMSG120N013MDG vs Alternatives

Comparison vs Si-only modules (practical trade-offs)

Against Si-only modules, the CMSG120N013MDG typically shows lower switching losses and improved efficiency at modestly higher switching frequencies, with comparable or slightly better conduction loss depending on current and temperature. For cost-constrained PFC stages, hybrids often hit an optimal point where efficiency gains justify incremental BOM complexity. Provide representative 50 kW inverter plots showing conduction and switching loss breakdowns to illustrate where hybrid topology yields system-level gains.

Comparison vs full SiC modules

Full SiC modules dominate at high switching frequencies and where power density is paramount: they deliver the lowest switching losses and enable simpler thermal management for the same power level, at the expense of higher device and gate-driver cost. Break-even analyses should consider switching frequency, system-level EMI mitigation costs, and lifecycle cost. Typical break-even comes when switching frequency and power density requirements drive system-level savings that offset higher SiC module cost.

Application-specific mini-case: PFC or inverter example

For a 5 kW PFC using the CMSG120N013MDG, expected efficiency gains vs Si-only designs are on the order of several percentage points depending on switching frequency; thermal design must accommodate the reduced continuous current at elevated junction temperatures, and gate-driver tuning should be validated to minimize EMI. A practical checklist: run double-pulse sweeps at target Vdc and Ipk, map device temperatures under expected duty, and verify EMI levels meet conducted and radiated limits.

6 — Design & Validation Checklist: From Prototype to Production

Pre-selection checklist for system architects

Architects should confirm rated current at target ambient, define thermal-management options (heatsink, liquid cooling), verify gate-driver compatibility and gate‑power budget, plan EMI mitigation and confirm module availability/lead times. Long-tail search phrases for documentation can include: “CMSG120N013MDG switching loss test” and “Si/SiC hybrid module selection checklist” to aid reproducibility and procurement alignment.

Prototype validation steps for power electronics engineers

Prototype steps: controlled double-pulse characterization with documented Rg, thermal mapping under mission power profiles, extended burn-in at representative ambient and duty, and EMC pre-checks. Define pass criteria (e.g., less than X% increase in VCE(sat) after Y cycles, maintained switching-energy limits) and implement logging cadence for burn-in and field tests to capture drift over time.

Deployment best practices & monitoring in the field

In-field recommendations include junction-temperature estimation via calibrated models or embedded sensors, periodic efficiency checks under defined loads, and event logging for overcurrent and overtemperature trips. Define maintenance intervals (e.g., annual thermal inspections, spare-module strategy based on mission-critical uptime) and maintain spare inventory informed by component lead times and failure-mode risk assessments.

Summary

The CMSG120N013MDG provides a cost-efficient Si/SiC hybrid path that balances conduction and switching trade-offs for many applications, but realizing those gains requires disciplined gate‑drive tuning, validated thermal design and standardized testing to quantify real-world performance. Engineers should focus on repeatable double-pulse characterization, thermal derating curves tied to their mission profile, and lifecycle cost comparisons versus full‑SiC at target switching frequencies to determine the optimal module choice. The report emphasizes measurable performance metrics so that design decisions are data-driven and reproducible.

• Run double-pulse tests with a standardized fixture to capture Eon/Eoff and dynamic dV/dt/dI/dt behavior for CMSG120N013MDG evaluation.
• Create thermal derating curves from steady-state and transient thermal mapping to translate 260 A @25°C to usable load at elevated temperatures.
• Compare lifecycle cost vs full‑SiC for your switching frequency and power density requirements to determine break-even points.

Common Questions

What are the most important performance metrics for evaluating CMSG120N013MDG?

Key metrics are conduction loss (VCE(sat) and Rds(on) vs temperature), switching energy (Eon/Eoff under controlled double‑pulse conditions), thermal resistances (Rth(j‑c), Rth(c‑a)), and SOA constraints such as short-circuit capability and thermal cycling endurance. Engineers should measure these under controlled and repeatable conditions and present normalized losses per kW for fair comparison.

How should engineers validate thermal derating for Si/SiC hybrid modules?

Validate derating by mapping junction-equivalent temperature vs maintained dissipated power at multiple ambient points (25°C, 75°C, 100°C) using infrared thermography and case thermocouples. Translate junction limits into maximum continuous current values with safety margins for mission duty cycles; add pulsed‑to‑continuous derating curves and verify against long-duration burn-in to catch solder fatigue or thermal‑coupling effects.

When is a full SiC module preferred over a hybrid like CMSG120N013MDG?

Full SiC becomes preferable when switching frequency, power density or efficiency targets create system-level savings that outweigh the higher device and gate-drive cost. If the application demands high-frequency hard-switching with minimal switching loss and maximum power density (e.g., compact traction inverters or high-frequency DC–DC converters), full SiC typically outperforms hybrids despite higher up-front cost.